Researcher Database

（Last updated : 2024-04-03 19:43:51）

FUJINO Takeshi

Department / Course College of Science and Engineering Department of Electronic and Computer Engineering

Title / Position Professor

Other Affiliations
1.	Graduate School of Science and Engineering
2.	Research Organization of Science and Technology VLSI Center
3.	Research Organization of Science and Technology Research Center for IoT Security

Academic background
1.	～1986	Master Course │ Electronic Science and Engineering │ Graduate School, Division of Engineering │ Kyoto University │ Completed
2.	1995/03 Degree Acquisition	│ Kyoto University Doctor of Engineering
3.	～1984	Department of Electronic Engineering │ Faculty of Engineering │ Kyoto University │ Graduated

Research activities
1.		Information Processing Society of Japan
2.		The Institute of Electronics, Information and Communication Engineers (IEICE)

Subject of research
1.	High-performance LSI Design Methodology utilizing EB direct writing
2.	embedded memory and systemLSI

Research summary
LSI Design Technologies that Target Network and Security Applications ・Tamper resistant cryptographic LSI design technology ・Manufacturing facilitator LSI design technology ・Variable logical LSI design technology ・LSI for network application design technology

Present specialized field
Keyword：Hardware security, Programmable Logic, Functional embedded memory, Network system

Papers
1.	2024/03/07	Model Extraction Attack without Natural Images │ 6th ACNS Workshop on Security in Machine Learning and its Applications (SiMLA) │ (Co-authored)
2.	2024/03/05	FPGA Implementation of Physically Unclonable Functions based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks │ 5th workshop on Artificial Intelligence in Hardware Security(AIHWS) │ (Co-authored)
3.	2024/03/01	A Feasibility Study of Data Poisoning against On-device Learning Edge AI by Physical Attack against Sensors │ RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,2024 │ (Co-authored)
4.	2024/03/01	Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface │ IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences │ E107-A (3),pp.344-354 (Co-authored)
5.	2024/03/01	Evaluation of Side-channel Attacks against Error Correction Circuit for Arbiter PUF │ RISP International Workshop on Nonlinear Circuits, Communications and Signal Processing,2024 │ (Co-authored)
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Academic conference presentation
1.	2019/04/17	PUF (Physical Unclonable Functions) devices for IoT applications (Photomask Japan 2019)
2.	2018/09/10	A Proposal of Efficient Error Recovery Method Utilizing Output Characteristics of CMOS Image Sensor PUF (Cryptographic Hardware and Embedded Systems (CHES) poster)
3.	2018/09/10	A Side-Channel Attack Method against Truncated MAC CAN Message based on AUTOSAR Specification (Cryptographic Hardware and Embedded Systems (CHES) poster)
4.	2017/08/29	A Proposal of PUF utilizing Pixel Variations in the CMOS Image Sensor (IWSEC 2017 (The 12th International Workshop on Security))
5.	2017/05/02	Malicious CAN-message Attack against Advanced Driving Assistant System (IEEE International Symposium on Hardware Oriented Security and Trust (HOST)2017)
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Winning science prize
1.	2020/03	Research Institute of Signal Processing Student Paper Award NCSP'20 (Black-Box Adversarial Attack Utilizing Quantized Probability Output against Deep Neural Network Classifier)
2.	2020/03	Research Institute of Signal Processing Student Paper Award NCSP'20 (Countermeasure against Backdoor Attack on Neural Networks Utilizing Knowledge Distillation)
3.	2014/03	The Research Institute of Signal Processing Best Paper Award on Journal of Signal Processing "Max-Plus Algebra-Based Morphological Wavelet Transform Watermarking for Highly-Parallel Processing with Mobile Embedded Processor
4.	2010/11	Best Paper Award on Proc. of 23rd International Conference on Computer Applications in Industry and Engineering, “Placement Tool Dedicated for a Via-programmable Logic Device VPEX”

Acquisition patent
1.	2010/07	Cryptographic Circuit using Tamper Resistant Memory circuit （PCT/JP2010/062689）